The inductive parasitics of the power delivery network (PDN) in digital PCBs can lead to switching noise at the power pins of integrated circuits. In order to mitigate that noise, designers usually place decoupling capacitors (decaps) between the power and the ground nets. As these capacitors result in additional cost and routing complexity, it is crucial to minimise the number used.
The decap tool that is included in CST PCB STUDIO® (CST PCBS) allows the optimization of the number and location of these capacitors in order to meet the specification in terms of target impedance within minutes, while controlling cost.
The field solver engine behind this optimization is the 3DFEM (PI) solver, which means that parasitic inductance and resistance as well as the connecting vias are considered accurately.